Vsd - Embedded-Uvm

[LeeAndro]

Last updated 6/2019MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHzLanguage: English | Size: 2.18 GB | Duration: 4h 6m

Opensource Verification and Emulation

What you'll learn
We take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC FPGA based Emulation
We learn how to code Embedded UVM powered testbench for a hardware accelerator design IP
The test bench is then adapted to Cyclone V and Ultrascale Zynq based platforms to demonstrate Embedded UVM powered low-cost SoCFPGA based emulation solutions.​

Requirements
Basics of UVM is nice to have
Basics of digital design is a must to have
Novice knowledge of opensource EDA flow is nice to have
Description
Of course, there is a requirement for open-source verification, but that's not the only thing we want to cater to. There are other verification trends and challenges which system Verilog and other verification platforms are not able to meet. So, we want to position Embedded-UVM for that. In the past decade or so, the major thing which is making verification tougher than it used to be, is the death of Moore's law.As far as processor frequency goes, it stabilizes at 4GHz and it's coming down as we move to multi-core processors. So, when you look at it from a simulation perspective, post-2005 it is becoming increasingly difficult to run simulations on bigger chips.Chip size keeps increasing, while processor speed is stagnant and hence, simulation is a limiting factor. Simulation speed is going to be limited unless we move to multi-core processors. Contemporary EDA tools run RTL simulations in a multi-core environment. System Verilog doesn't run in a multi-core environment.Therefore, test-bench runs on one thread and RTL runs on multiple threads. RTL is more formal in nature, in sense, it can be synthesized, it can be partitioned, different partitions can run on different processors, while test-bench is behavioral in nature and it cannot be partitioned the way RTL can be.About Speakeruneet Goel is a 1994 graduate in Electronics from Punjab Eeering College. He has 24 years of experience in the VLSI industry where he worked for Sro, Motorola, Texas Instruments and TranSwitch.For the past 8 years, he has been working for Coverity Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

Overview

Section 1: Introduction

Lecture 1 Introduction

Lecture 2 Introduction to FPGA boards to be used in webinar

Lecture 3 Introduction to E-UVM framework using adder example

Lecture 4 Testcase and E-UVM

Section 2: Verification trends and challenges

Lecture 5 Verification perfomance and introduction to FOSSI

Lecture 6 Variation trends and challenges of data network and compute performance

Lecture 7 Testbenches for system level verification and hardware accelerators

Lecture 8 Hardware accelerators from verification perspective

Lecture 9 Hardware accelerators perspective Embedded - UVM

Lecture 10 LIVE QnA with participants about E-UVM multi-threading

Lecture 11 LIVE QnA regarding system-C comparison with E-UVM

Section 3: Embedded UVM and Multicore testbenches

Lecture 12 Introduction to Embedded-UVM

Lecture 13 Embedded-UVM innovation - Multicore UVM

Lecture 14 Multicore E-UVM implementation

Section 4: Productivity and Emulation Features

Lecture 15 Productivity features and interfacing with RTL simulations

Lecture 16 Embedded UVM powered emulation

Lecture 17 Testbench simulation demo with Avalon streaming bus as DUT

Lecture 18 OSI model of communication and UVM transaction explanation

Section 5: Embedded UVM Testbench Architecture and Environment

Lecture 19 Testbench architecture and verilog co-simulation

Lecture 20 Steps and importance of Randomizing object and cloning

Lecture 21 Typical UVM environment comparison in Embedded-UVM and system verilog

Lecture 22 LIVE QnA with webinar participants regarding E-UVM environment

Lecture 23 avst_keccak protocol

Section 6: The DUT - SHA3 core

Lecture 24 Functional details, control & status, data map, output and input

Lecture 25 SHA3 core testbench understanding and running

Lecture 26 LIVE demo on DE10-Nano Cyclone V FPGA board

Lecture 27 LIVE code debug and emulation

Section 7: Assignments and Conclusion

Lecture 28 Assignment explanation and conclusion

Lecture 29 Assignment testcase

Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology,Professional UVM eeers keen to know about multi-threaded testbench simulation technology,Anyone looking to learn new opensource technology and be ahead of market

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