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VSD - Library characterization and modelling - Part 1

LeeAndro

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Trusted Editor
VSD - Library characterization and modelling - Part 1
h264, yuv420p, 1280x720 |ENGLISH, 48000 Hz, 2channels | 4h 54mn | 546 MB

If you are STA eeer or PNR eeer or CTS eeer or, in general, a physical designer or Synthesis eeer, you must have definitely come across the word 'Library'.


VLSI - The heart of STA, PNR, CTS and Crosstalk
What you'll learn

Understand timing, noise and power libraries syntax and semantics

Develop models for logic gates and macros

Use the above generated models and do STA

Requirements

Full knowledge on circuit design and SPICE simulations

Full knowledge on custom layout

Nice to have knowledge on Physical design, Static timing analysis, Noise & Crosstalk and Clock tree synthesis

You can refer to my existing courses or any other external material, but knowledge about above all is a must

Description

This course explains you, in detail, what it exactly means.

You can call Library as the soul and heart of Sonductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete.

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes.

Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA

I would like to Thank complete Paripath team for helping me in designing expents for this course. This course is motivated by desire to fill gap on characterization and modelling

Trademark:

Liberty is a registered trademark of Synopsys Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SDF and SPEF are trademarks of Open Verilog International

Get in right now and have an unforgettable journey of your life...

Happy Learning!!

Who this course is for:

Research professionals

Graduate students

Circuit and PDK designers

Characterization eeers

CAD developers

Managers, Mentors and the merely curious



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