Writing UVM testbenches for Newbie

[LeeAndro]

MP4 | Video: h264, 1280x720 | Audio: AAC, 44100 Hz
Language: English | Size: 3.62 GB | Duration: 10h 47m

Usage of the Base Classes viz.

What you'll learn

Writing testbenches in UVM

Understanding usage of Configuration db in UVM

Strats for implementation of UVM components such as Transaction, Generator, Sequencer, Monitor, Scoreboard, Environment, Test

Usage of TLM ports for Communication between Driver , Sequencer, Monitor, Scoreboard

Usage of Reporting Mechanism in UVM

Usage of Virtual Interface

UVM_Object and UVM_Component

Pure Lab-based course with minimum focus on theoretical aspects of UVM

Requirements

Some exposure to Verilog and System Verilog

Description

Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification eeers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on fog a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification eeers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.

The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.

Who this course is for:

Anyone interested in learning Design Verification Testbenches with UVM

FPGA Verification Eeer Aspirants




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