Aldec ALINT-PRO 2021.09 | 904.0 mb
Aldec, Inc.
, a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development dramatically by identifying design issues early in the development schedule.
for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.
Aldec ALINT-PRO
2021.09.1933 *
x64 english
PC **
904.0 mb
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