Published 11/2025
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English | Size: 1.08 GB | Duration: 2h 0m
CPU design RTL to Simulation
What you'll learn
Design a fully functional Single-Cycle RISC-V processor from scratch using Verilog HDL that can run your C program.
Understand the complete instruction execution flow - from fetch and decode to execute, memory access, and write-back.
Implement and simulate key hardware modules including ALU, Register File, Control Unit, and Memory using Icarus Verilog and GTKWave.
Decode and execute RV32I instructions and understand the bit-level structure of RISC-V ISA formats (R, I, S, B, U, and J).
Integrate all components into a top-level CPU design and verify its functionality with custom testbenches.
Gain the confidence to extend your design into pipelined or SoC-based architectures for advanced projects.
Requirements
Basic understanding of digital electronics
Some familiarity with Verilog HDL syntax
Description
Ever wondered how a CPU works at the signal level - not just conceptually, but truly inside?This course is your step-by-step guide to building your own Single-Cycle RISC-V processor from scratch, using Verilog and industry-style RTL design methods.We'll start from the fundamentals - understanding the RISC-V ISA, instruction formats, and architecture flow - and gradually move toward creating a complete working CPU core capable of executing instructions, handling memory, and performing control operations.By the end of this course, you'll not only have a fully functional single-cycle RISC-V CPU, but also a deep understanding of processor internals - knowledge that directly translates into real-world RTL design and verification roles. What You'll LearnDesign and implement a Single-Cycle RISC-V processor in VerilogUnderstand the RISC-V instruction formats and dataflow architectureCreate and integrate key modules - ALU, Control Unit, Register File, Memory, and moreWrite testbenches to simulate and verify your CPU's functionalityGain industry-level exposure to RTL design flow and debugging techniques Tools & EnvironmentVerilog (any simulator: ModelSim, Vivado, or online tools like EDA Playground)RISC-V ISA referenceA text editor and logic-level curiosity Who Is This Course ForStudents and engineers interested in VLSI, RTL design, or computer architectureAnyone who wants to build, not just learn about, a CPUBeginners looking for a clear, hands-on start in RISC-V and digital designHardware enthusiasts who want to connect architecture theory with real implementation
Project builders or research students looking for a strong foundation before designing a pipelined or SoC-based processor.,If you've ever wondered how a CPU executes your code, this course is for you
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