Digital IC/FPGA Design P3:Common Used Hardware Architectures
Published 12/2024
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 1.1 GB | Duration: 2h 39m
a big step towards complex IP design
What you'll learn
Behavior of SRAM and usage suggestions
Handshake interface and synchronous FIFO
Pipeline to maximal clock frequency
Arbiter
Cross clock domain (CDC) and asynchronous FIFO
Ping-Pong
Pipeline with control (feedback)
Pipeline with hazard and forward path
Slide window
Requirements
Basic knowledge of digital fundamental
Basic C or C++ programing language
Basic Verilog Language
Description
In this chapter I will introduce common used hardware architectures, including:1: Behavior of SRAM and usage suggestions;2: Handshake interface and synchronous FIFO;3: Pipeline to maximal clock frequency;4: Arbiter;5: Cross clock domain (CDC) and asynchronous FIFO;6: Ping-Pong;7: Pipeline with control (feedback);8: Pipeline with hazard and forward path;9: Slide window;These are useful architectures engineer used to deal with complex designs, such as RISC-V CPU core, AI accelerator and so on. To help you mastering them, I will assign a coding exercise after each section.This is chapter 3 of whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.
Who this course is for
Senior undergraduate students of EE or higher
IC design/verification engineers with 0~2 year experience
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