Mentor Graphics ModelSim SE-64 2019.4

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Mentor Graphics ModelSim SE-64 2019.4 | 793.8 mb
Mentor, a Siemens business, is pleased to announce the availability of ModelSim 2019.4, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.

New Features Contained in this Release:
- Improved VHDL performance defaults
- Legacy -novopt option is no longer supported


General Defects Repaired in 2019.4
- [nodvtid] - vmake many now consume less memory.
- QSIM-55252 - The vdir command can now be given the name of an already-existing directory; it will transform the directory into a Questa library. The directory must be empty for this to succeed.
SystemVerilog Defects Repaired in 2019.4
- [nodvtid] - Vlog would crash when parsing certain syntax constructs.
- QSIM-58023 - Using a wire type with a struct containing a field of an enum type could generate an error like

# ** Fatal: (vsim-3355) Variable 'struct1.enum1' cannot be converted to a net.

- [nodvtid] - SystemVerilog macros undefining and subsequently redefining a macro of the same name repeatedly during macro expansion would generate incorrect results.
- QSIM-58670 - Vsim incorrectly reported a vsim-3837 error for multiple continuous assignments to a variable when using a bit-select expression with a complex index expression
VHDL Defects Repaired in 2019.4
- QSIM-57546 - If a package contains a package instance within a USE clause, static array constraints within the package instance may not be compiled correctly, possible causing a fatal internal error during elaboration of the design by the simulator.
- QSIM-57795 - The compiler could report a fatal internal error if it encountered a generic declaration list with an index constraint within a generic vector preceding an interface package.
- QSIM-58539 - (results) The attributes INSTANCE_NAME and PATH_NAME, were not considered globally static. If the prefix of the attribute is a signal and this expression appears in a wait statement with an on clause or in a concurrent statement other than a process, a change in signal value would trigger a evaluation of the wait or concurrent statement. This currently results in extra statement executions. The attributes are now considered globally static, so the wait or concurrent statement is no longer sensitized to that prefix. This change can cause simulation results to be different from previous versions.
- QSIM-57830 - Using unconstrained alias signal as an actual for a port connection was leading to a crash. This has been fixed.
- QSIM-57969 - (results) Using a function call without arguments in a generic map was showing syntax error incorrectly. This has been fixed.
- QSIM-60023 - Use of the -mixedsvvh switch could result in the compiler erroneously emitting error vcom-1995, which states that a package cannot be imported into SystemVerilog designs. This can occur when at least two VHDL packages are compiled on a single command-line with the -mixedsvvh switch; and, one package contains a constant declaration initialized by a function defined in the other package, and the name of the first package comes lexically before the name of the second package.
- QSIM-57712 - If an entity has a generic whose type depends on a previously declared generic and that entity is directly instantiated, then vsim could crash when loading the design. The work around was to use a component instantiation.
- QSIM-60153 - If a component had a port that is a multi-dimensional array whose bounds depended on the component's generics and the port's actual was an expression, vcom could generate an internal error.



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