Mentor Graphics QuestaSim 2020.1

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Mentor Graphics QuestaSim 2020.1 | 677.3 mb
Mentor, a Siemens business, is pleased to announce the availability of QuestaSim 2020.1 comprehensive platform for verification complex designs. Questa is built on a core simulation and debug engine providing the industry's most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF.

Release Notes for QuestaSim 2020.1 - Date: Jan 28 2020
New Features Contained in this Release:
- Improved SystemVerilog performance, syntax support, extensions
- Improved VHDL performance defaults
- SystemC 2.3.2 support and default
- Visualizer Debug high performance and capacity (VIS)
- Coverage - adaptive exclusions, multibit expressions, FSM, toggle improved
- Coverage - new reporting switch from 10.7x is now default
- Legacy -novopt option is no longer supported




QuestaSim is part of the Questa Advanced Functional Verification Platform and is the latest tool in Mentor Graphics tool suite for Functional Verification. The tool provides simulation support for latest standards of SystemC, SystemVerilog, Verilog 2001 standard and VHDL. This tool is an advancement over Modelsim in its support for advanced Verification features like coverage databases, coverage driven verification, working with assertions, SystemVerilog constrained-random functionality.[/center]